1. Field of the Invention
The present invention relates to a bit synchronization extraction circuit used for bit synchronization in an integrated service digital network (ISDN) line interface connected to a reference point S/T of an ISDN basic user network interface, and more particularly relates to a bit synchronization extraction circuit which is dependent on frame synchronization.
The bit synchronization extraction is included in an ISDN line interface which is included in an ISDN terminal equipment (TE) connected through the reference point S/T to a network termination (NT).
In the ISDN terminal equipment (TE), to enable smooth bidirectional communication, the transmitting signal must be synchronized with the received signal. To this end, the bit synchronization extraction circuit generates a bit timing signal which is synchronized with the received signal. The bit timing signal is used as a clock signal for the transmitting signal.
In the bit synchronization extraction circuit, it is desirable that the timing extraction jitter be as small as possible, and that the bit timing be stable in the presence of line noise.
According to the recommendation of CCITT, the bit timing extraction jitter in the transmitting signal with respect to the received signal must be within .+-.7 percent of the bit period.
2. Description of the Related Art
Conventionally, there are two types of bit synchronization extraction circuits, i.e., a counter preset mode circuit and a digital phase locked loop (DPLL) mode circuit.
The conventional counter preset mode circuit has an advantage of a short time for extraction of the bit synchronization, but had the disadvantage of being sensitive against line noise and having a large timing extraction jitter.
Conventional DPLL mode has the advantage of also being resistant to line noise and having small timing extraction jitter, but has the disadvantage of taking a long time for bit synchronization extraction. That is, the amount of correction until establishment of bit synchronization could be 2.6 .mu.s (5.2 .mu.s/2) in the worst case. There is the disadvantage of the long time taken for establishment of bit synchronization due to the correction of this in steps of less than 0.36 .mu.s (5.2 .mu.s.times.0.07). For example, if correction is made in steps of 0.16 .mu.s, 16 steps of correction (2.6 .mu.s.div.0.16 .mu.s) is required until establishment of bit synchronization. Therefore, if there were eight protection stages, points of change of data of 128 bits (16 steps.times.8 stages) would be required. Since there are four points of change of data in the 48 bits of one frame (250 .mu.s) in the minimum case, the maximum time for establishment of synchronization would be 8 ms (128 bits/4.times.250 .mu.s).
The ISDN terminal equipment uses the bit timing extracted by the bit synchronization extraction circuit for transmiting data to the line. To ensure the restriction in transmitting data, i.e., to ensure a bit timing jitter within .+-.7 percent (0.36 .mu.s), the latter DPLL mode has been used, since the restriction cannot be met by the former.